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LXT386LE Datasheet(PDF) 17 Page - Intel Corporation

Part # LXT386LE
Description  QUAD T1/E1/J1 Transceiver
PDF  78 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT386LE Datasheet(HTML) 17 Page - Intel Corporation

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QUAD T1/E1/J1 Transceiver — LXT386
Datasheet
17
N12
55
TNEG3/
UBS3
DI
DI
Transmit Negative Data.
Unipolar/Bipolar Select.
N13
56
TPOS3/
TDATA3
DI
DI
Transmit Positive Data.
Transmit Data.
N14
57
TCLK3
DI
Transmit Clock.
K12
58
LOS2
DO
Loss of Signal.
M12
59
RNEG2/
BPV2
DO
DO
Receive Negative Data.
Bipolar Violation Detect.
M13
60
RPOS2/
RDATA2
DO
DO
Receive Positive Data.
Receive Data.
M14
61
RCLK2
DO
Receive Clock.
L12
62
TNEG2/
UBS2
DI
DI
Transmit Negative Data.
Unipolar/Bipolar Select.
L13
63
TPOS2/
TDATA2
DI
DI
Transmit Positive Data.
Transmit Data.
L14
64
TCLK2
DI
Transmit Clock.
K13
80
INT
DO
Interrupt. This active Low, maskable, open drain output requires an
external 10k pull up resistor. If the corresponding interrupt enable bit is
enabled, INT goes Low to flag the host when the LXT386 changes state
(see details in the interrupt handling section). The microprocessor INT
input should be set to level triggering.
K14
81
ACK/
RDY/
SDO
DO
DO
DO
Data Transfer acknowledge (Motorola Mode).
Ready (Intel mode).
Serial Data Output (Serial Mode).
Motorola Mode
A Low signal during a databus read operation indicates that the
information is valid. A Low signal during a write operation acknowledges
that a data transfer into the addressed register has been accepted
(acknowledge signal).Wait states only occur if a write cycle immediately
follows a previous read or write cycle (e.g. read modify write).
Intel Mode
A High signal acknowledges that a register access operation has been
completed (Ready Signal). A Low signal on this pin signals that a data
transfer operation is in progress. The pin goes tristate after completion of
a bus cycle.
Serial Mode
If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low,
SDO is valid on the falling edge of SCLK. This pin goes into high Z state
during a serial port write access.
Table 1.
Pin Assignments and Signal Descriptions (Continued)
Ball #
PBGA
Pin #
LQFP
Symbol
I/O1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
2. N/C means “Not Connected”



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