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LXT386LE Datasheet(PDF) 61 Page - Intel Corporation |
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LXT386LE Datasheet(HTML) 61 Page - Intel Corporation |
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61 / 78 page  QUAD T1/E1/J1 Transceiver — LXT386 Datasheet 61 Table 45. JTAG Timing Characteristics Parameter Sym Min Typ Max Unit Test Conditions Cycle time Tcyc 200 - - ns J-TMS/J-TDI to J-TCK rising edge time Tsut 50 - - ns J-CLK rising to J-TMS/L-TDI hold time Tht 50 - - ns J-TCLK falling to J-TDO valid Tdod - - 50 ns Figure 20. JTAG Timing Table 46. Intel Mode Read Timing Characteristics Parameter2 Sym Min Typ1 Max Unit Test Conditions Address setup time to latch Tsalr 10 –– ns Valid address latch pulse width Tvl 30 –– ns Latch active to active read setup time Tslr 10 –– ns Chip select setup time to active read Tscsr 0 –– ns Chip select hold time from inactive read Thcsr 0 –– ns Address hold time from inactive ALE Thalr 5 ns Active read to data valid delay time Tprd 10 – 50 ns Address setup time to RD inactive Thar 1 –– ns Address hold time from RD inactive Tsar 5 –– ns Inactive read to data tri-state delay time Tzrd 3 – 35 ns Valid read signal pulse width Tvrd 60 –– ns Inactive read to inactive INT delay time Tint –– 10 ns Active chip select to RDY delay time Tdrdy 0 – 12 ns Active ready Low time Tvrdy –– 40 ns Inactive ready to tri-state delay time Trdyz –– 3ns 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. tCYC tSUR tHT tDOD TCK TMS TDI TDO |
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