LXT386LE datasheet(12/78 Pages) INTEL

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LXT386 — QUAD T1/E1/J1 Transceiver

Datasheet

Protected Monitoring/Address Select Inputs.

Hardware Mode

In hardware mode these pins are used to select a specific port for non

intrusive monitoring. During protection monitoring receiver 0 inputs are

internally connected to a specific transmit or receive port. Receiver 0

routes the data from the selected port to its data and clock recovery

circuits. The data on the monitor port can be routed to TTIP0/TRING0 by

activating the remote loopback for channel 0 (TCLK0 must be active in

order for this operation to take place). In addition, the recovered clock and

data can be observed at the RCLK0/RPOS0/RNEG0 outputs.

If A0-A3 are Low, the LXT386 is configured as a quad line transceiver

without monitoring capability.

Transmitter monitoring is not supported when the respective channel is set

to analog loopback mode.

Host Mode

In non-multiplexed host mode, these pins function as non-multiplexed

address pins.

Table 1.

Pin Assignments and Signal Descriptions (Continued)

Ball #

PBGA

Pin #

LQFP

Symbol

I/O1

Description

1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;

N.C.: Not Connected.

2. N/C means “Not Connected”

Selection

No Protection Monitoring

Receiver 1

Receiver 2

Receiver 3

Reserved

No Protection Monitoring

Transmitter 1

Transmitter 2

Transmitter 3

Reserved

LXT386LE Datasheet(PDF) 12 Page - Intel Corporation

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