LXT386LE datasheet(24/78 Pages) INTEL

24 / 78 page

LXT386 — QUAD T1/E1/J1 Transceiver

Datasheet

3.2.1

Loss of Signal Detector

The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal

detection circuit. It is independent of its internal data slicer comparators and complies to the latest

ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be

configured to comply to the ETSI ETS 300 233 specification (LACS Register). In hardware mode,

the LXT386 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation.

The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented

each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the

operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is

replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is

required for receive operation. When the LOS condition is cleared, the LOS flag is reset and

another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the

data content at the receiver input during the entire LOS detection period for that channel.

3.2.1.1

E1 Mode

In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32 consecutive

pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit

period) with no more than 15 consecutive zeros and the signal level exceeds 250mV (typical), the

LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK.

In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048

consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when

the incoming signal has transitions when the signal level is equal or greater than 250mV for more

than 32 consecutive pulse intervals. This mode is activated by setting the LACS register bit to one.

If it is necessary to use AIS with LOS, see errata 10.3 for a way to implement this.

3.2.1.2

T1 Mode

The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for

175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse

density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a

pulse. The incoming signal is considered to have transitions when the signal level is equal or

greater than 250mV.

3.2.1.3

Data Recovery Mode

In data recovery mode the LOS digital timing is derived from a internal self timed circuit. RPOS/

RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775

recommendation. The LXT386 monitors the incoming signal amplitude. Any signal below 200mV

for more than 30

µs (typical) will assert the corresponding LOS pin. The LOS condition is cleared

when the signal amplitude rises above 250mV. The LXT386 requires more than 10 and less than

255 bit periods to declare a LOS condition in accordance to ITU G.775.

3.2.2

Alarm Indication Signal (AIS) Detection

The AIS detection is performed by the receiver independent of any loopback mode. This feature is

available in host mode only. Because there is no clock in data recovery mode, AIS detection will

not work in that mode. AIS requires MCLK to have clock applied, since this function depends on

the clock to count the number of ones in an interval.

LXT386LE Datasheet(PDF) 24 Page - Intel Corporation

LXT386LE Datasheet(HTML) 24 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL