LXT386LE datasheet(63/78 Pages) INTEL

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QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

Figure 22. Multiplexed Intel Read Timing

Table 47. Intel Mode Write Timing Characteristics

Parameter2

Sym

Min

Typ1

Max

Unit

Test Conditions

Address setup time to latch

Tsalw

––

Valid address latch pulse width

Tvl

––

Latch active to active write setup time

Tslw

––

Chip select setup time to active write

Tscsw

––

Chip select hold time from inactive write

Thcsw

––

Address hold time from inactive ALE

Thalw

Data valid to write active setup time

Tsdw

––

Data hold time to active write

Thdw

––

Address setup time to WR inactive

Thaw

––

Address hold time from WR inactive

Tsaw

––

1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.

2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.

3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset

Operation and Host Mode sections for more information.

ALE

RDY

Tristate

ADDRESS

AD7-AD0

DATA OUT

tVL

tSLR

tSCSR

tVRD

tHSCR

tPRD

tZRD

tINT

tRDYZ

tVRDY

tDRDY

tSALR

tHALR

INT

LXT386LE Datasheet(PDF) 63 Page - Intel Corporation

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