LXT386LE datasheet(51/78 Pages) INTEL

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QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

5.5.3

Instruction Register (IR)

The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted

LSB first. Table 33 shows the valid instruction codes and the corresponding instruction description.

Table 32. Analog Port Scan Register (ASR)

ASR Control Code

AT1 Forces Voltage To:

AT2 Senses Voltage From:

11111

TTIP0

TRING0

11110

TTIP1

TRING1

11101

TTIP2

TRING2

11100

TTIP3

TRING3

11011

Reserved

11010

Reserved

11001

Reserved

11000

Reserved

10111

RTIP0

RRING0

10110

RTIP1

RRING1

10101

RTIP2

RRING2

10100

RTIP3

RRING3

10011

Reserved

10010

Reserved

10001

Reserved

10000

Reserved

Table 33. Instruction Register (IR)

Instruction

Code #

Comments

EXTEST

000

Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR.

Output pins values are loaded from the BSR.

INTEST_ANALOG

010

Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and

AT2. Refer to Table 32.

SAMPLE / PRELOAD

100

Connects the BSR to TDI and TDO. The normal path between the LXT386 logic and

the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins.

IDCODE

110

Connects the IDR to the TDO pin.

BYPASS

111

Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass

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