CLRC663 datasheet(23/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

8.4.2.2 Read data

To read out data from the CLRC663 by using the SPI compatible interface, the following byte order has to be

used.

The first byte that is sent defines the mode (LSB bit) and the address.

byte 0

byte 1

byte 2

byte 3 to n-1

byte n

byte n+1

MOSI

address 0

address 1

address 2

……..

address n

00h

MISO

data 0

data 1

……..

data n - 1

data n

Table 17. Byte Order for MOSI and MISO

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.3 Write data

To write data to the CLRC663 using the SPI interface, the following byte order has to be used. It is possible to

write more than one byte by sending a single address byte (see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

byte 0

byte 1

byte 2

3 to n-1

byte n

byte n + 1

MOSI

address 0

data 0

data 1

……..

data n - 1

data n

MISO

……..

Table 18. Byte Order for MOSI and MISO

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.4 Address byte

The address byte has to fulfill the following format:

The LSB bit of the first byte defines the used mode. To read data from the CLRC663, the LSB bit is set to logic

1. To write data to the CLRC663, the LSB bit has to be cleared. The bits 6 to 0 define the address byte.

NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is written to address [address

byte], [data1] is written to address [address byte + 1] and [data2] is written to [address byte + 2].

Exception: This auto increment of the address byte is not performed if data is written to the FIFO address

address 6

address 5

address 4

address 3

address 2

address 1

address 0

1 (read)

0 (write)

MSB

LSB

Table 19. Address byte 0 register; address MOSI

8.4.2.5 Timing Specification SPI

The timing condition for SPI interface is as follows:

Symbol

Parameter

Min

Typ

Max

Unit

tSCKL

SCK LOW time

Table 20. Timing conditions SPI

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

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