CLRC663 datasheet(51/177 Pages) NXP

51 / 177 page

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

fout = 13.56 MHz × PLLDiv_FB /PLLDiv_Out

Frequency [MHz]

1.8432

3.6864

PLLDiv_FB

PLLDiv_Out

206

103

accuracy [%]

0.04

0.03

0.04

0.08

0.04

0.08

0.04

0.01

Table 45. Divider values for selected frequencies using the integerN PLL

8.8.3 Low Frequency Oscillator (LFO)

The CLRC663 family implements an Low-Frequency Oscillator (LFO). Timer T4 can be configured to use a

clock generated by this LFO as input clock, and can be configured as wakeup counter. As wakeup counter, the

timer T4 allows to wake up the system in regular time intervals which allows to design a reader that is regularly

polling for card presence or implements a low-power card detection (LPCD).

The LFO is trimmed during chip production to run at 16 kHz. Unless a high accuracy of the LFO is required by

the application, and the device is operated in an environment with changing ambient temperatures, trimming of

the LFO is not required. For a typical application making use of the LFO for wake-up from power saving mode,

the trim value set during production can be used.

Optional trimming to achieve a higher accuracy of the 16 kHz LFO clock is supported by a digital state machine

which compares LFO-clock to a reference clock generated by the connected 27.12Mhz crystal. As reference

clock frequency for trimming of the LFO, a 13.56 MHz clock (27.12Mhz divided by 2 ) input clock to one of the

timers T0,T1,T2 or T3 is used.

One of the timers T0,T1,T2,T3 with an input clock of 13,56 MHz crystal clock is used to count one clock period

of the LFO. For an LFO Clock running at 16KHz this would result in 848 wakeup timer clocks of timer Tx (T0,

T1, T2, T3). Therefrore, the timer count value Tx at the end of a trimming cycle is expected to be 176 (wakeup

timer is counting down: 1023-848=175, +/- 1 tolerance is accepted). The trim cycle is executed once in the

T4 timer cycle. Therefore the T4 autoload value shall be bigger than 0x05 to ensure that one trimming cycle

takes place before T4 expires. The Tx timer value is reloaded to 1023 during the start of an Auto trim cycle. This

happens every time, once after the T4 timer underflows.

At the end of each trim cycle, the timer value is checked:

• Timer Tx value < 174: LFO Frequency is too low and the trim value is incremented by 1 on T4 Timer event

• Timer Tx value > 176: LFO Frequency is too high and the trim value is decremented by 1 on T4 Timer event

• Timer Tx value is within 174 and 176: LFO Frequency = 16 KHz and trimming procedure is stopped

The cycle proceeds until the autotrimm function is stopped (Timer Tx value is within 174 and 176).

In addition, the trimming cycle can be aborted by sending an IDLE Command from the host to cancel the current

command execution. T3 is not allowed to be used in case T4AutoLPCD is set in parallel. It is not required to

configure a TXStart condition with underflow. The T0/1/2/3 timer will typically not underflow. It may happen if the

LPO clock is very slow, but it is not required to take an action to generate this event.

8.9 Power management

8.9.1 Supply concept

The CLRC663 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD (Transmitter Power Supply).

These three voltages are independent from each other.

To connect the CLRC663 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be at a level of 3.3 V,

TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at TVDD results in a higher field strength.

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

51 / 177

CLRC663 Datasheet(PDF) 51 Page - NXP Semiconductors

CLRC663 Datasheet(HTML) 51 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL