CLRC663 datasheet(50/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Address 0 (8)

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

0x02

0x00

0x01

0x00

0x08

0xB2

Table 43. Register reset values (Hex.)(Page1 and page 2)...continued

8.8 Clock generation

8.8.1 Crystal oscillator

The clock applied to the CLRC663 acts as time basis for generation of the carrier sent out at TX and for the

quadrature mixer I and Q clock generation as well as for the coder and decoder of the synchronous system.

Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest

performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator

buffer with the recommended circuitry.

001aam308

27.12 MHz

XTAL1 XTAL2

READER IC

Figure 32. Crystal connection

Symbol

Parameter

Conditions

Min

Typ

max

Unit

fxtal

crystal frequency

27.12

MHz

Δfxtal/fxtal

relative crystal frequency

variation

-250

+250

ppm

ESR

equivalent series resistance

100

load capacitance

Pxtal

crystal power dissipation

100

μW

Table 44. Crystal requirements recommendations

8.8.2 IntegerN PLL clock line

The CLRC663 is able to provide a clock with configurable frequency at CLKOUT from 1 MHz to 24 MHz

(PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a microcontroller which avoids the need of

a second crystal oscillator in the reader system. Clock source for the IntegerN-PLL is the 27.12 MHz crystal

oscillator.

Two dividers are determining the output frequency. First a feedback integer-N divider configures the VCO

frequency to be N × fin/2 (control signal pll_set_divfb). As supported Feedback Divider Ratios are 23, 27 and

28, VCO frequencies can be 23 × fin / 2 (312 MHz), 27 × fin / 2 (366 MHz) and 28 × fin / 2 (380 MHz).

The VCO frequency is divided by a factor which is defined by the output divider (pll_set_divout). The following

table shows the accuracy achieved for various frequencies (integer multiples of 1 MHz and some typical RS232

frequencies) and the divider ratios to be used. The register bit ClkOutEn enables the clock at CLKOUT pin.

The following formula can be used to calculate the output frequency:

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

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