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CLRC663 Datasheet(PDF) 99 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 99 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Bit
7
6
5
4
3
2
1
0
Symbol
LPCD_TX_HIGH
LPCD_FILTER
LPCD_Q_
UNSTABLE
LPCD_I_UNSTABLE
Access
rights
RFU
-
r/w
r/w
r
r
Table 191. LPCD_Options register (address 3Ah)
Bit
Symbol
Description
7 to 4
RFU
-
3
LPCD_TX_HIGH
If set, the TX-driver will be the same as VTVDD during LPCD. This will allow for
a better LPCD detection range (higher transmitter output voltage) at the cost of
a higher current consumption. If this bit is cleared, the output voltage at the TX
drivers will be = TVDD- 0.4V. If this bit is set, the output voltage at the TX drivers
will be = VTVDD.
2
LPCD_FILTER
If set, The LPCD decision is based on the result of a filter which allows to
remove noise from the evaluated signal in I and Q channel. Enabling LPCD_
FILTER allows compensating for noisy conditions at the cost of a longer RF-ON
time required for sampling. The total maximum LPCD sampling time is 4.72us.
1
LPCD_Q_UNSTABLE
If bit 2 of this register is set, bit 1 indicates that the Q-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER (bit
2) = 1. This information can be used by the host application for configuration of
e.g. the threshold LPCD_QMax or inverting the TX drivers.
0
LPCD_I_UNSTABLE
If bit 2 of this register is set, bit 0 Indicates that the I-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER
(bit2) = 1. This information can be used by the host application for configuration
of e.g. the threshold LPCD_IMax or inverting the TX drivers.
Table 192. LPCD_Options
9.15 Pin configuration
9.15.1 PadEn
Bit
7
6
5
4
3
2
1
0
Symbol
SIGIN_
EN / OUT7
CLKOUT_
EN / OUT6
IFSEL1_
EN / OUT5
IFSEL0_
EN / OUT4
TCK_EN /
OUT 3
TMS_EN /
OUT2
TDI_EN /
OUT1
TDO_EN /
OUT0
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 193. PadEn register (address 44h)
Bit
Symbol
Description
7
SIGIN_EN / OUT7
Enables the output functionality on SIGIN (pin 5). The pin is then used as
output.
6
CLKOUT_EN / OUT6
Enables the output functionality of the CLKOUT (pin 22). The pin is then used
as output. The CLKOUT function is switched off.
Table 194. PadEn bits
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
99 / 177



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