CLRC663 datasheet(30/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Having performed this write access, the read access starts. The host sends the device address of the

CLRC663. As an answer to this device address, the CLRC663 responds with the content of the addressed

enables a fast transfer of register content. The address pointer is incremented automatically and data is read

from the locations [address], [address+1], [address+2]... [address+(n-1)]

In order to support a fast FIFO data transfer, the address pointer is not incremented automatically in case the

address is pointing to the FIFO.

The read/write bit shall be set to logic 1.

001aam305

Ack

(W)

Ack

I2C slave address

A7-A0

Frontend IC register

address A6-A0

Ack

DATA

[7..0]

[0..n]

Ack

(W)

Ack

Optional, if the previous access was on the same register address

Read Cycle

Write Cycle

I2C slave address

A7-A0

Frontend IC register

address A6-A0

(R)

Ack

sent by master

sent by slave

I2C slave address

A7-A0

Ack

DATA

[7..0]

[0..n]

0..n

Nack

DATA

[7..0]

Figure 22. Register read and write access

8.4.4.9 I2CL-bus interface

The CLRC663 provides an additional interface option for connection of a SAM. This logical interface fulfills

the I2C specification, but the rise/fall timings will not be compliant to the I2C standard. The I2CL interface uses

standard I/O pads, and the communication speed is limited to 5 MBaud. The protocol itself is equivalent to the

fast mode protocol of I2C. The SCL levels are generated by the host in push/pull mode. The RC663 does not

stretch the clock. During the high period of SCL, the status of the line is maintained by a bus keeper.

The address is 01010xxb, where the last two bits of the address can be defined by the application. The

definition of these bits can be done by two options. With a pin, where the higher bit is fixed to 0 or the

configuration can be defined via EEPROM. Refer to the EEPROM configuration in Section 8.7.

Parameter

Min

Max

Unit

fSCL

MHz

tHD;STA

tLOW

100

Table 26. Timing parameter I2CL

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

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