 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CLRC663 Datasheet(PDF) 11 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
CLRC663 Datasheet(HTML) 11 Page - NXP Semiconductors |
|
|
11 / 177 page  NXP Semiconductors CLRC663 High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus 8 Functional description 001aam005 I2C, LOGICAL FIFO 512 Bytes REGISTERS STATEMACHINES EEPROM 8 kByte SPI SAM interface VOLTAGE REGULATOR 3/5 V => 1.8 V DVDD POR ADC PLL LFO RX OSC TX VOLTAGE REGULATOR 3/5 V => 1.8 V AVDD RNG ANALOGUE FRONT-END BOUNDARY SCAN IF0 IFSEL0 IFSEL1 IF1 IF2 IF3 TCK TDI TMS TDO RESET LOGIC PDOWN I2C UART SPI host interfaces INTERRUPT CONTROLLER IRQ SIGIN TIMER0..3 CRC TIMER4 (WAKE-UP TIMER) SIGPRO TX CODEC RX DECOD CL- COPRO SIGIN/ SIGOUT CONTROL SIGOUT VMID RXN RXP TX1 TX2 XTAL1 XTAL2 SDA SCL VDD VSS PVDD TVDD TVSS AUX1 AUX2 AVDD DVDD CLKOUT Figure 3. Detailed block diagram of the CLRC663 8.1 Interrupt controller The interrupt controller handles the enabling/disabling of interrupt requests. All of the interrupts can be configured by firmware. Additionally, the firmware has possibilities to trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0 and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt controller register is implemented. The CLRC663 indicates certain events by setting bit IRQ in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. Table 4. shows the available interrupt bits, the corresponding source and the condition for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer underflows. The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interrupt bit automatically. The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is detected. CLRC663 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.3 — 3 January 2024 11 / 177 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
