CLRC663 datasheet(24/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Symbol

Parameter

Min

Typ

Max

Unit

tSCKH

SCK HIGH time

th(SCKH-D)

SCK HIGH to data input hold time

tsu(D-SCKH)

data input to SCK HIGH set-up time

th(SCKL-Q)

SCK LOW to data output hold time

t(SCKL-NSSH)

SCK LOW to NSS HIGH time

tNSSH

NSS HIGH time

Table 20. Timing conditions SPI...continued

aaa-016093

tSCKL

tNSSH

tSCKH

tSCKL

tsu(D-SCKH)

th(SCKH-D)

th(SCKL-Q)

t(SCKL-NSSH)

SCK

MOSI

MISO

MSB

LSB

NSS

Figure 13. Connection to host with SPI

Remark: To send more bytes in one data stream, the NSS signal must be LOW during the send process. To

send more than one data stream, the NSS signal must be HIGH between each data stream.

8.4.3 RS232 interface

8.4.3.1 Selection of the transfer speeds

The internal UART interface is compatible to an RS232 serial interface. The levels supplied to the pins are

between VSS and PVDD. To achieve full compatibility of the voltage levels to the RS232 specification, an

RS232 level shifter is required.

Table 22 describes examples for different transfer speeds and relevant register settings. The resulting transfer

speed error is less than 1.5 % for all described transfer speeds. The default transfer speed is 115.2 kbit/s.

To change the transfer speed, the host controller has to write a value for the new transfer speed to the register

SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set the transfer speed in the SerialSpeedReg.

Table 21 describes the settings of BR_T0 and BR_T1.

BR_T0

factor BR_T0

Table 21. Settings of BR_T0 and BR_T1

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

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