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CLRC663 Datasheet(PDF) 96 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 96 Page - NXP Semiconductors |
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96 / 177 page  NXP Semiconductors CLRC663 High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus Bit 1 Bit 0 Division 0 0 23 (VCO frequency 312 MHz) 0 1 27 (VCO frequency 366 MHz) 1 0 28 (VCO frequency 380 Mhz) 1 1 23 (VCO frequency 312 Mhz) Table 177. Setting of feedback divider PLLDiv_FB [1:0] 9.13.4 PLLDiv_Out Bit 7 6 5 4 3 2 1 0 Symbol PLLDiv_Out Access rights r/w Table 178. PLLDiv_Out register (address 3Eh) Bit Symbol Description 7 to 0 PLLDiv_Out PLL output divider factor; refer to Section 8.8.2. Table 179. PLLDiv_Out bits Value Division 0 RFU 1 RFU 2 RFU 3 RFU 4 RFU 5 RFU 6 RFU 7 RFU 8 8 9 9 10 10 ... ... 253 253 254 254 255 255 Table 180. Setting for the output divider ratio PLLDiv_Out [7:0] CLRC663 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.3 — 3 January 2024 96 / 177 |
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