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CLRC663 Datasheet(PDF) 66 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 66 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
9.4.4 FIFOData
In- and output of FIFO buffer. Contrary to any read/write access to other addresses, reading or writing to the
FIFO address does not increment the address pointer. Writing to the FIFOData register increments, reading
decrements the number of bytes present in the FIFO.
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOData
Access
rights
dy
dy
dy
dy
dy
dy
dy
dy
Table 61. FIFOData register (address 05h);
Bit
Symbol
Description
7 to 0
FIFOData
Data input and output port for the internal FIFO buffer. Refer to Section 8.5.
Table 62. FIFOData bits
9.5 Interrupt configuration registers
The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid the unintended
modification of bits.
The mechanism of changing register contents requires the following consideration: IRQ(x).Set indicates, if a set
bit on position 0 to 6 shall be cleared or set. Depending on the content of IRQ(x).Set, a write of a 1 to positions
0 to 6 either clears or sets the corresponding bit. With this register, the application can modify the interrupt
status which is maintained by the CLRC663.
Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written to a bit position 6...0
will trigger the setting or clearance of this bit as defined by bit 7. Example: writing FFh sets all bits 6..0, writing
7Fh clears all bits 6..0 of the interrupt request register
9.5.1 IRQ0 register
Interrupt request register 0.
Bit
7
6
5
4
3
2
1
0
Symbol
Set
HiAlertIRQ LoAlertIRQ
IdleIRQ
TxIRQ
RxIRQ
ErrIRQ
RxSOF
IRQ
Access
rights
w
dy
dy
dy
dy
dy
dy
dy
Table 63. IRQ0 register (address 06h); reset value: 00h
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 6..0 sets the interrupt request
0: Writing a 1 to a bit position 6..0 clears the interrupt request
6
HiAlertIRQ
Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRQ stores
this event.
Table 64. IRQ0 bits
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
66 / 177



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