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CLRC663 Datasheet(PDF) 27 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 27 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
The following features defined by the NXP Semiconductors I2C interface specification, rev. 3.0, June 2007 are
not supported:
• The CLRC663 I2C interface does not stretch the clock
• The CLRC663 I2C interface does not support the general call. This means that the CLRC663 does not
support a software reset
• The CLRC663 does not support the I2C device ID
• The implemented interface can only act in slave mode. Therefore no clock generation and access arbitration
is implemented in the CLRC663.
• High-speed mode is not supported by the CLRC663
001aam000
READER IC
SDA
SCL
PULL-UP
NETWORK
PULL-UP
NETWORK
MICROCONTROLLER
Figure 16. I2C-bus interface
The voltage level on the I2C pins is not allowed to be higher than PVDD.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor. Both lines SDA and SCL
are set to HIGH level if no data is transmitted. Data on the I2C-bus can be transferred at data rates of up to 400
kbit/s in fast mode, up to 1 Mbit/s in the fast mode+.
If the I2C interface is selected, a spike suppression according to the I2C interface specification on SCL and SDA
is automatically activated.
For timing requirements, refer to Table 256.
8.4.4.2 I2C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state or LOW state of the
data line shall only change when the clock signal on SCL is LOW.
001aam300
data line stable;
data valid
change
of data
allowed
SDA
SCL
Figure 17. Bit transfer on the I2C-bus
8.4.4.3 I2C START and STOP conditions
To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined.
A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH.
The master always generates the START and STOP conditions. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
27 / 177



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