PCA9641PW datasheet(26/55 Pages) NXP

26 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

26 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

12.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 12).

12.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the

STOP condition (P) (see Figure 13).

12.3 System configuration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 14).

Fig 12. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Definition of START and STOP conditions

mba608

SDA

SCL

STOP condition

START condition

PCA9641PW Datasheet(PDF) 26 Page - NXP Semiconductors