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PCA9641PW Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCA9641PW Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 55 page ![]() PCA9641 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2.1 — 27 October 2015 5 of 55 NXP Semiconductors PCA9641 2-channel I2C-bus master arbiter 6. Pinning information 6.1 Pinning 6.2 Pin description [1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. Fig 2. Pin configuration for TSSOP16 Fig 3. Pin configuration for HVQFN16 INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS PCA9641PW 002aag815 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 VDD INT_IN SDA_SLAVE SCL_SLAVE AD3 AD2 AD1 AD0 002aag816 Transparent top view SDA_MST1 AD2 SCL_MST1 AD3 RESET SCL_SLAVE SCL_MST0 SDA_SLAVE 4 9 3 10 2 11 1 12 terminal 1 index area PCA9641BS Table 3. Pin description Symbol Pin Description TSSOP16 HVQFN16 INT0 1 15 active LOW interrupt output 0 (external pull-up required) SDA_MST0 2 16 serial data master 0 (external pull-up required) SCL_MST0 3 1 serial clock master 0 (external pull-up required) RESET 4 2 active LOW reset input (external pull-up required) SCL_MST1 5 3 serial clock master 1 (external pull-up required) SDA_MST1 6 4 serial data master 1 (external pull-up required) INT1 7 5 active LOW interrupt output 1 (external pull-up required) VSS 86[1] supply ground AD0 9 7 address input 0 (externally held to VSS, VDD, pull-up to VDD or pull-down to VSS) AD1 10 8 address input 1 (externally held to VSS, VDD, pull-up to VDD or pull-down to VSS) AD2 11 9 address input 2 (externally held to VSS, VDD, pull-up to VDD or pull-down to VSS) AD3 12 10 address input 3 (externally held to VSS, VDD, pull-up to VDD or pull-down to VSS) SCL_SLAVE 13 11 serial clock slave (external pull-up required) SDA_SLAVE 14 12 serial data slave (external pull-up required) INT_IN 15 13 active LOW interrupt input (external pull-up required) VDD 16 14 supply voltage |
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