C8051F360 datasheet(115/288 Pages) SILABS

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Rev. 1.0

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C8051F360/1/2/3/4/5/6/7/8/9

10.5. External Interrupts

The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-

tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or

active low; the IT0 and IT1 bits in TCON (Section “21.1. Timer 0 and Timer 1” on page 248) select level or

edge sensitive. The table below lists the possible configurations.

Active low, edge sensitive

Active high, edge sensitive

Active low, level sensitive

Active high, level sensitive

/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 10.7).

Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and

/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin

via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the

selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section

“17.1. Priority Crossbar Decoder” on page 185 for complete details on configuring the Crossbar).

IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external

interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-

sponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.

When configured as level sensitive, the interrupt-pending flag remains logic ‘1’ while the input is active as

defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic ‘0’ while the input is inac-

tive. The external interrupt source must hold the input active until the interrupt request is recognized. It

must then deactivate the interrupt request before execution of the ISR completes or another interrupt

request will be generated.

IT0

IN0PL

/INT0 Interrupt

IT1

IN1PL

/INT1 Interrupt

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