C8051F360 datasheet(183/288 Pages) SILABS

183 / 288 page

Rev. 1.0

183

C8051F360/1/2/3/4/5/6/7/8/9

17. Port Input/Output

Digital and analog resources are available through up to 39 I/O pins. On the largest devices

(C8051F360/3), port pins are organized as four byte-wide Ports and one 7-bit-wide Port. On the other

devices (C8051F361/2/4/5/6/7/8/9), port pins are three byte-wide Ports and one partial port. Each of the

Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; Port pins P0.0–P3.7 can

be assigned to one of the internal digital resources as shown in Figure 17.3. The designer has complete

control over which functions are assigned, limited only by the number of physical I/O pins. This resource

assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a

Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.

The Crossbar assigns the selected internal digital resources to the I/O pins based on the peripheral priority

order of the Priority Decoder (Figure 17.3 and Figure 17.4). The registers XBR0 and XBR1, defined in SFR

Definition 17.1 and SFR Definition 17.2, are used to select internal digital functions.

All Port I/Os are 5 V tolerant (refer to Figure 17.2 for the Port cell circuit). The Port I/O cells are configured

as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Com-

plete Electrical Specifications for Port I/O are given in Table 17.1 on page 201.

XBR0, XBR1,

PnSKIP Registers

Digital

Crossbar

Priority

Decoder

I/O

Cells

P0.0

P0.7

P0MASK, P0MATCH

P1MASK, P1MATCH,

P2MASK, P2MATCH

Registers

UART

Highest

Priority

Lowest

Priority

SYSCLK

SMBus

T0, T1

PCA

CP0

CP1

Outputs

SPI

(P0.0-P0.7)

(P1.0-P1.7)

(P2.0-P2.7)

PnMDOUT,

PnMDIN Registers

3.5–3.7 available on

C8051F360/3

(P3.0-P3.7)

I/O

Cells

P1.0

P1.7

I/O

Cell

P2.0

P2.7

I/O

Cells

P3.0

P3.7

3.1–3.4 available on

C8051F360/1/3/4/6/8

Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3)

C8051F360 Datasheet(PDF) 183 Page - Silicon Laboratories

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