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C8051F360 Datasheet(PDF) 182 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 182 Page - Silicon Laboratories |
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182 / 288 page ![]() Table 16.3. PLL Frequency Characteristics –40 to +85 °C unless otherwise specified. Input Frequency (Divided Reference Frequency) PLL Output Frequency *Note: The maximum operating frequency of the C8051F366/7/8/9 is 50 MHz. C8051F360/1/2/3/4/5/6/7/8/9 182 Rev. 1.0 Table 16.4. PLL Lock Timing Characteristics –40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units 530 MHz 25 100* MHz Input Frequency Multiplier (Pll0mul) Pll0flt Setting Output Frequency Min Typ Max Units 5 MHz 20 0x0F 100 MHz 202 µs 13 0x0F 65 MHz 115 µs 16 0x1F 80 MHz 241 µs 9 0x1F 45 MHz 116 µs 12 0x2F 60 MHz 258 µs 6 0x2F 30 MHz 112 µs 10 0x3F 50 MHz 263 µs 5 0x3F 25 MHz 113 µs 25 MHz 40x01 100 MHz 42 µs 2 0x01 50 MHz 33 µs 3 0x11 75 MHz 48 µs 2 0x11 50 MHz 17 µs 2 0x21 50 MHz 42 µs 1 0x21 25 MHz 33 µs 2 0x31 50 MHz 60 µs 1 0x31 25 MHz 25 µs |
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