C8051F360 datasheet(181/288 Pages) SILABS

181 / 288 page

Rev. 1.0

181

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 16.8. PLL0MUL: PLL Clock Scaler

Bits 7–0: PLLN7–0: PLL Multiplier.

These bits select the multiplication factor of the divided PLL reference clock. When set to

any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set

to ‘00000000b’, the multiplication factor will be equal to 256.

SFR Page:

SFR Address:

0xB1

R/W

Reset Value

PLLN7

PLLN6

PLLN5

PLLN4

PLLN3

PLLN2

PLLN1

PLLN0

00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Definition 16.9. PLL0FLT: PLL Filter

Bits 7–6: UNUSED. Read = 00b. Write = don’t care.

Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.

Selection is based on the desired output frequency, according to the following table:

Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.

Selection is based on the divided PLL reference clock, according to the following table:

All other states of PLLLP3–0 are RESERVED.

SFR Page:

SFR Address:

0xB2

R/W

Reset Value

–

PLLICO1 PLLICO0

PLLLP3

PLLLP2

PLLLP1

PLLLP0 00110001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PLL Output Clock

PLLICO1-0

65–100 MHz

45–80 MHz

30–60 MHz

25–50 MHz

Divided PLL Reference Clock

PLLLP3-0

19–30 MHz

0001

12.2–19.5 MHz

0011

7.8–12.5 MHz

0111

5–8 MHz

1111

C8051F360 Datasheet(PDF) 181 Page - Silicon Laboratories

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