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C8051F360 Datasheet(PDF) 185 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 185 Page - Silicon Laboratories |
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185 / 288 page ![]() Rev. 1.0 185 C8051F360/1/2/3/4/5/6/7/8/9 17.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 17.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which will be assigned to specific port pins (P0.1 and P0.2 in the C8051F360/3 devices, P0.4 and P0.5 in the C8051F361/2/4/5/6/7/8/9 devices). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to the port pins associated with the external oscillator, VREF, external CNVSTR signal, IDA0, and any selected ADC or comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 17.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP, P3SKIP = 0x00); Figure 17.4 shows the Crossbar Decoder priority with the P1.0 and P1.1 pins skipped (P1SKIP = 0x03). 01234567012345670123456701234 567 (*4-Wire SPI Only) CP0 CP0A CP1 CP1A /SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI T0 T1 00000000000000000000000000000 000 P3 P3SKIP[0:7] P3.1-P3.4 available on 32/48-pin only P3.5-P3.7 available on 48-pin only P2 P2SKIP[0:7] (48-pin package) (32-pin and 28-pin packages) P0 P1 P1SKIP[0:7] NSS* SCK MISO MOSI RX0 SF Signals (32- and 28- pin) PIN I/O TX0 SF Signals (48-pin) TX0 RX0 SDA P0SKIP[0:7] SCL Figure 17.3. Crossbar Priority Decoder with No Pins Skipped |
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