C8051F360 datasheet(180/288 Pages) SILABS

180 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

180

Rev. 1.0

To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external

clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.

Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL-

PWR bits can be cleared at the same time.

SFR Definition 16.6. PLL0CN: PLL Control

Bits 7–5: UNUSED. Read = 000b. Write = don’t care.

Bit 4:

PLLLCK: PLL Lock Flag.

0: PLL Frequency is not locked.

1: PLL Frequency is locked.

Bit 3:

RESERVED. Read = 0b. Must Write 0b.

Bit 2:

PLLSRC: PLL Reference Clock Source Select Bit.

0: PLL Reference Clock Source is Internal Oscillator.

1: PLL Reference Clock Source is External Oscillator.

Bit 1:

PLLEN: PLL Enable Bit.

0: PLL is held in reset.

1: PLL is enabled. PLLPWR must be ‘1’.

Bit 0:

PLLPWR: PLL Power Enable.

0: PLL bias generator is de-activated. No static power is consumed.

1: PLL bias generator is active. Must be set for PLL to operate.

SFR Page:

SFR Address:

0xB3

R/W

Reset Value

–

PLLLCK

Reserved

PLLSRC

PLLEN

PLLPWR 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Definition 16.7. PLL0DIV: PLL Pre-divider

Bits 7–5: UNUSED. Read = 000b. Write = don’t care.

Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider.

These bits select the pre-divide value of the PLL reference clock. When set to any non-zero

value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’,

the reference clock will be divided by 32.

SFR Page:

SFR Address:

0xA9

R/W

Reset Value

–

PLLM4

PLLM3

PLLM2

PLLM1

PLLM0

00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

C8051F360 Datasheet(PDF) 180 Page - Silicon Laboratories

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