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C8051F360 Datasheet(PDF) 195 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 195 Page - Silicon Laboratories |
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195 / 288 page ![]() Rev. 1.0 195 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.14. P1MASK: Port1 Mask Bits 7–0: P1MASK[7:0]: Port1 Mask Value. These bits select which Port pins will be compared to the value stored in P1MAT. 0: Corresponding P1.n pin is ignored and cannot cause a Port Match event. 1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT. SFR Page: SFR Address: 0 0xE2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Definition 17.15. P2: Port2 Bits 7–0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. SFR Page: SFR Address: all pages 0xA0 (bit addressable) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 |
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