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C8051F360 Datasheet(PDF) 211 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 211 Page - Silicon Laboratories |
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211 / 288 page ![]() Table 18.3. Sources for Hardware Changes to SMB0CN • A START is generated. • A STOP is generated. • Arbitration is lost. • START is generated. • SMB0DAT is written before the start of an SMBus frame. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • A START followed by an address byte is received. • Must be cleared by software. • A STOP is detected while addressed as a slave. • Arbitration is lost due to a detected STOP. • A pending STOP is generated. • A byte has been received and an ACK response value is needed. • After each ACK cycle. • A repeated START is detected as a MASTER when STA is low (unwanted repeated START). • SCL is sensed low while attempting to gener- ate a STOP or repeated START condition. • SDA is sensed low while transmitting a ‘1’ (excluding ACK bits). • Each time SI is cleared. • The incoming ACK value is low (ACKNOWLEDGE). • The incoming ACK value is high (NOT ACKNOWLEDGE). • A START has been generated. • Lost arbitration. • A byte has been transmitted and an ACK/NACK received. • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. • Must be cleared by software. Rev. 1.0 211 C8051F360/1/2/3/4/5/6/7/8/9 Bit Set by Hardware When: Cleared by Hardware When: MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI |
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