C8051F360 datasheet(209/288 Pages) SILABS

209 / 288 page

Rev. 1.0

209

C8051F360/1/2/3/4/5/6/7/8/9

18.4.2. SMB0CN Control Register

SMB0CN is used to control the interface and to provide status information (see SFR Definition 18.2). The

higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to

jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive

modes, respectively.

STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus

interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-

ter. Writing a ‘1’ to STA will cause the SMBus interface to enter Master Mode and generate a START when

the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a ‘1’ to STO

while in Master Mode will cause the interface to generate a STOP and end the current transfer after the

next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be

generated.

As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit

indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating

that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing

value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit

before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;

however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further

slave events will be ignored until the next START is detected.

The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface

is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-

tion. ARBLOST is cleared by hardware each time SI is cleared.

The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or

when an arbitration is lost; see Table 18.3 for more details.

Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and

the bus is stalled until software clears SI.

Table 18.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 18.4 for SMBus sta-

tus decoding using the SMB0CN register.

C8051F360 Datasheet(PDF) 209 Page - Silicon Laboratories