C8051F360 datasheet(206/288 Pages) SILABS

206 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

206

Rev. 1.0

18.4.1. SMBus Configuration Register

The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,

select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is

set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the

INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,

the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit

is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of

the current transfer).

Table 18.1. SMBus Clock Source Selection

The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or

when the Free Timeout detection is enabled. When operating as a master, overflows from the selected

source determine the absolute minimum SCL low and high times as defined in Equation 18.1. Note that the

selected clock source may be shared by other peripherals so long as the timer is left running at all times.

For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer

configuration is covered in Section “21. Timers” on page 247.

THighMin

TLowMin

fClockSourceOverflow

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Equation 18.1. Minimum SCL High and Low Times

The selected clock source should be configured to establish the minimum SCL High and Low times as per

Equation 18.1. When the interface is operating as a master (and SCL is not driven or extended by any

other devices on the bus), the typical SMBus bit rate is approximated by Equation 18.2.

BitRate

fClockSourceOverflow

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Equation 18.2. Typical SMBus Bit Rate

SMBCS1

SMBCS0

SMBus Clock Source

Timer 0 Overflow

Timer 1 Overflow

Timer 2 High Byte Overflow

Timer 2 Low Byte Overflow

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