C8051F360 datasheet(204/288 Pages) SILABS

204 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

204

Rev. 1.0

The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set

to logic ‘1’ to indicate a "READ" operation and cleared to logic ‘0’ to indicate a "WRITE" operation.

All transactions are initiated by a master, with one or more addressed slave devices as the target. The

master generates the START condition and then transmits the slave address and direction bit. If the trans-

action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time

waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the

data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master

generates a STOP condition to terminate the transaction and free the bus. Figure 18.3 illustrates a typical

SMBus transaction.

SLA6

SDA

SLA5-0

R/W

D6-0

SCL

Slave Address + R/W

Data Byte

START

ACK

NACK

STOP

Figure 18.3. SMBus Transaction

18.3.1. Arbitration

A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL

and SDA lines remain high for a specified time (see Section “18.3.4. SCL High (SMBus Free) Timeout” on

page 205). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-

tion scheme is employed to force one master to give up the bus. The master devices continue transmitting

until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be

pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning

master continues its transmission without interruption; the losing master becomes a slave and receives the

rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and

no data is lost.

18.3.2. Clock Low Extension

SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different

speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow

slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line

LOW to extend the clock low period, effectively decreasing the serial clock frequency.

18.3.3. SCL Low Timeout

If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,

the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus

protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than

25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-

cation no later than 10 ms after detecting the timeout condition.

When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to

reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to

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