TMPR3911 datasheet(57/462 Pages) TOSHIBA

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Chapter 2 Pin Descriptions

2-3

WE*:

OUTPUT

This pin is used as the write signal for the system. This signal is asserted for writes to MCS3-0*,

CS3-0*, CARD2CS* and CARD1CS* for memory and attribute space, and for writes to DRAM

and SDRAM.

CAS0* (WE0*):

OUTPUT

This pin is used as the CAS signal for SDRAMs, the CAS signal for D[7:0] for DRAMs, and the

write enable signal for D[7:0] for static devices.

CAS1* (WE1*):

OUTPUT

This pin is used as the CAS signal for D[15:8] for DRAMs and the write enable signal for

D[15:8] for static devices.

CAS2* (WE2*):

OUTPUT

This pin is used as the CAS signal for D[23:16] for DRAMs and the write enable signal for

D[23:16] for static devices. Also used as the bank select signal for SDRAM (applies only to

TMPR3912XB-92/AU-92)

CAS3* (WE3*):

OUTPUT

This pin is used as the CAS signal for D[31:24] for DRAMs and the write enable signal for

D[31:24] for static devices.

RAS0*:

OUTPUT

This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs.

RAS1* (DCS1*):

OUTPUT

This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1

DRAMs.

DCS0*:

OUTPUT

This pin is used as the chip select signal for Bank0 SDRAMs.

DCKE:

OUTPUT

This pin is used as the clock enable for SDRAMs.

TMPR3911 Datasheet(PDF) 57 Page - Toshiba Semiconductor