TMPR3911 datasheet(95/462 Pages) TOSHIBA

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Chapter 3 CPU Module

3-11

3.3.6.6

Virtual Memory and the TLB

Mapped virtual addresses are translated into physical addresses using a Translation Lookaside

Buffer (TLB). The TLB is a fully associative memory device that holds 32 entries to provide

mapping of 32 4 Kbyte pages. When address mapping is indicated (that is, when the access is in

kuseg or kseg2), each TLB entry is simultaneously checked for a match with the extended virtual

address.

The CPU supports up to four coprocessors. Coprocessor 0 (CP0), which is called the System

Control Coprocessor, is implemented as an integral part of the TX39/H. CP0 supports address

translation, exception handling, and other “privileged” operations. It consists of the 32-entry TLB

plus the ten registers shown in Figure 3.3.4. The sections that follow describe how each of the four

TLB-related registers is used. (Note: CP0 functions and registers associated with exception

handling are described in Chapter 6 of the 32-Bit TX System RISC TX39 Family Architecture

manual.)

CP0 & the TLB

PRld

BadVA

EPC

Cause

Context

Status

Random

Index

(“Safe” entries)

(See Random Register)

TLB

EntryLo

EntryHi

Config

Figure 3.3.4 The CP0 Registers & the TLB

3.3.6.7

TLB Entries

Each TLB entry is 32 bits wide and its format is shown in Figure 3.3.5 Each of the fields of a

TLB entry has a corresponding field in the EntryHi/EntryLo register pair described next. Refer to

Figure 3.3.6 for a description of each of the TLB entry fields.

V G

PFN

PID

VPN

Figure 3.3.5 Format of a TLB Entry

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