TMPR3911 datasheet(63/462 Pages) TOSHIBA

Part #	TMPR3911

Description	32-Bit TX System RISC TX39 Family

PDF	462 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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Chapter 2 Pin Descriptions

2-9

2.2.8

Power Module Pins

ONBUTN:

INPUT

Asserting this signal will cause PWRCS to be asserted if the PWROK signal is high.

PWRCS:

OUTPUT

This signal is asserted automatically if the ONBUTN signal is asserted when the PWROK signal

is high. Clearing the PWRCS bit in the Power Control Register by software deasserts this signal.

PWROK:

INPUT

This pin should be asserted when the source of power is stable.

When the PWROKNMI bit in the Interrupt Status 6 Register is set, the deassertion of the

PWROK signal causes the NMI (Non Maskable Interrupt).

PWRINT:

INPUT

The rising edge and falling edge of signal to this pin causes PWRINT interrupt request.

VCC3:

INPUT

This pin should be asserted when the source of power for external circuit is stable.

Asserting this pin starts oscillating the internal clock.

For more details of these pins, see chapter 12.

TMPR3911 Datasheet(PDF) 63 Page - Toshiba Semiconductor