TMPR3911 datasheet(90/462 Pages) TOSHIBA

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Chapter 3 CPU Module

3-6

3.3.4

DMA Arbitration

The DMA arbiter allows the SIU to launch DMA transactions to the BIU. The SIU will initiate a

DMA transaction by pulsing the SStart signal. Once this occurs, the DMA arbiter will assert the DMA

Request signal to the CPU core. The CPU core will then assert the DMA Grant signal to indicate that

the CPU is now idling. If the SIU is performing a DMA write (as indicated by the SWrite signal), the

SAddr, SData and SByteEn signals will then be loaded into the Write Buffer once there is space

available in the Write Buffer. As soon as the Write Buffer loads the signals, the DMA Arbitration logic

will assert the SAck signal to indicate to the SIU that the DMA write is complete.

At the same time that the data is loaded into the Write Buffer, the Snoop signal is asserted to the CPU

core. The snoop logic in the CPU core will invalidate the cache locations defined by the SAddr bits

when the Snoop signal is asserted. This provides cache coherency during DMA to simplify managing

the cache.

For a DMA read transaction, the SRead signal will be asserted by the SIU. The Write Buffer will

always be flushed before allowing the DMA read to begin. Once the Write Buffer is empty, the DMA

read will begin and the SAck signal will be asserted to end the DMA read once the BIU asserts the Ack

signal. The SIU will receive data input via the DataIn bus. The SBurst signal from the SIU is used to

initiate burst reads. The SIU will only request 4-word bursts, thus the BurstLen signals will be set to a

burst length of 4 whenever the SBurst signal is asserted during DMA reads.

3.3.5

CPU Stop Mode

In order to reduce the power dissipation in the CPU core, the clock to the CPU core can be disabled.

This is possible since the CPU core designs are implemented as fully static. The CPU core will

normally be in Stop Mode and will only be active to process interrupts. The CPU enters to the CPU

Stop Mode by setting the STOPCPU control bit in the Power Control Register. The STOPCPU control

bit will go to the DMA Arbitration logic, which will assert DMA Request to the CPU core upon the

STOPCPU signal being asserted. Once the CPU core responds with a DMA Grant, the DMA arbiter

will assert a signal FSTOPCPU that is given to the Clock Generator to disable the clock to the CPU

core.

TMPR3911 Datasheet(PDF) 90 Page - Toshiba Semiconductor