TMPR3911 datasheet(86/462 Pages) TOSHIBA

86 / 462 page

Chapter 3 CPU Module

3-2

3.2

CPU Core

3.2.1

Description

There are several enhancements for the PDA system. These additional key features of the CPU core

are:

•

Translation Look-aside Buffer (TLB) (4 Kbyte Page size, 32 Entries)

•

4 Kbyte instruction cache (I-cache)

•

16 bytes (4 words) per line (256 lines total)

•

physical address tag per cache line

•

single valid bit per cache line

•

programmable burst size (16 bytes to 128 bytes)

•

instruction streaming mode supported

•

direct-mapped

•

1 Kbyte data cache (D-cache)

•

4 bytes (1 word) per line (128 lines total)

•

physical address tag per cache line

•

single valid bit per cache line

•

programmable burst size (16 bytes to 128 bytes); burst refill can be disabled

•

write-through

•

two-way set associative

•

cache address snoop mode supported for DMA

•

× 32 on-chip hardware multiplier

•

supports 32

× 32 (single-cycle) multiplier operations, with 64-bit accumulator

•

signed or unsigned data formats

•

accumulator supports sign-extension and overflow status

•

existing multiply instructions are enhanced and new multiply and add instructions are added

to the MIPS I instruction set to improve the performance of DSP applications

TMPR3911 Datasheet(PDF) 86 Page - Toshiba Semiconductor

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