TMPR3911 datasheet(74/462 Pages) TOSHIBA

74 / 462 page

Chapter 2 Pin Descriptions

2-20

2.4

Pin Assignment

2.4.1

Pin assignment (in case of TMPR3912AU-92 and TMPR3912XB-92)

Table 2.4.1 Pin Assignment (1/3)

LQFP NO.

(TMPR3912)

FBGA

NO.

I/O

Signal

Name

LQFP NO.

(TMPR3912)

FBGA

NO.

I/O

Signal

Name

1A1



VDD

I/O

MIOX[0]

I/O

D[0] (D[24])

I/O

IO[6]

3E5



VSS

I/O

IO[5]

I/O

D[1] (D[25])



VSS

I/O

D[2] (D[26])

I/O

CHICLK

6E4



VDD

I/O

CHIFS

I/O

D[3] (D[27])

CHIDIN

8D3



VSS

CHIDOUT

I/O

D[4] (D[28])



VDD



VDD

RXD

I/O

D[5] (D[29])

TXD

I/O

D[6] (D[30])

I/O

IO[4]



VSS



I/O

D[7] (D[31])

IRIN



VSS

IROUT

I/O

D[8] (D[16])



VSS



VDD



VDD

I/O

D[9] (D[17])

CARDET

I/O

D[10] (D[18])

RXPWR



VSS

I/O

IO[3]

I/O

D[11] (D[19])

I/O

IO[2]



VDD



VSS

I/O

D[12] (D[20])

SPICLK

I/O

D[13] (D[21])

SPIIN



VSS

SPIOUT

I/O

D[14] (D[22])



VDD

I/O

D[15] (D[23])

TESTCPU



VDD

TESTIN

ENDIAN

VIDDONE

I/O

MIOX[1]

TESTAIU

MBUSINT



VSS

I/O

MBUSDATA

VCC3



VSS

BC32K

I/O

MBUSCLK



VDD



VDD

C32KlN



VDD

C32KOUT

SIBMCLK



VSS



VSS

PWRCS

SIBSCLK

PWRlNT

SIBSYNC

PWROK

SIBDIN



SIBDOUT

ONBUTN



VDD

PON*

SIBIRQ

R10

CPURES*

<NOTE>

(1)

* Active-low signal

(2)

( ) indicates the signal name in the little endian mode

(3)

The signal name change regarding DQMH/L is applied only to TMPR3912AU-92.

TMPR3911 Datasheet(PDF) 74 Page - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 74 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL