TMPR3911 datasheet(61/462 Pages) TOSHIBA

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Chapter 2 Pin Descriptions

2-7

2.2.4

CHI Pins

CHIFS:

INPUT/OUTPUT

This pin is the CHI frame synchronization signal. This pin is available for use in one of two

modes. As an output, this pin allows the TMPR3911/12 to be the master CHI sync source. As an

input, this pin allows an external peripheral to be the master CHI sync source and the

TMPR3911/12 CHI module will slave to this external sync.

CHICLK:

INPUT/OUTPUT

This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output,

this pin allows the TMPR3911/12 to be the master CHI clock source. As an input, this pin allows

an external peripheral to be the master CHI clock source and the TMPR3911/12 CHI module will

slave to this external clock.

CHIDOUT:

OUTPUT

This pin is the CHI serial data output signal.

CHIDIN:

INPUT

This pin is the CHI serial data input signal.

2.2.5

IO Pins

IO[6:0]:

INPUT/OUTPUT

These pins are general purpose input/output ports. Each port can be independently programmed

as an input or output port. Each port can generate a separate positive and negative edge interrupt.

Each port can also be independently programmed to use a 16 to 24 ms debouncer.

MFIO[1:0]:

INPUT/OUTPUT

These pins are multi-function input/output ports. Each port can be independently programmed as

an input or output port, or can be programmed for multi-function use to support test signals (for

debugging purposes only). Each port can generate a separate positive and negative edge interrupt.

Note that 30 other multi-function pins are available for usage as multi-function input/output ports.

These pins are named after their respective standard/normal function and are not listed here.

TMPR3911 Datasheet(PDF) 61 Page - Toshiba Semiconductor