TMPR3911 datasheet(11/462 Pages) TOSHIBA

11 / 462 page

Table of Contents

vii

16.1.1

Related Pins...........................................................................................................................................16-1

16.2

Overall Operation .........................................................................................................................................16-2

16.2.1

Power On/Off ........................................................................................................................................16-2

16.2.2

Baud Rate and Communication Parameters ..........................................................................................16-2

16.2.3

Interrupt Operation................................................................................................................................16-3

16.2.4

DMA Operation ....................................................................................................................................16-5

16.2.5

Internal Loopback .................................................................................................................................16-6

16.3

Transmitter Operation...................................................................................................................................16-7

16.3.1

Transmitter Pulse Output Operation......................................................................................................16-8

16.3.2

Transmitter Disable Operation ..............................................................................................................16-8

16.3.3

Transmitter BREAK Operation .............................................................................................................16-8

16.3.4

Transmitter Overrun ..............................................................................................................................16-8

16.4

Receiver Operation .......................................................................................................................................16-9

16.4.1

Receiver BREAK Operation ...............................................................................................................16-10

16.4.2

Receiver Frame Error Condition .........................................................................................................16-10

16.4.3

Receiver Overrun Condition ...............................................................................................................16-10

16.4.4

Receiver Parity Error Condition..........................................................................................................16-10

16.4.5

Receiver Pulse Operation ....................................................................................................................16-10

16.5

UART Registers..........................................................................................................................................16-11

16.5.1

UART Control 1 Register....................................................................................................................16-11

16.5.2

UART Control 2 Register....................................................................................................................16-14

16.5.3

UART DMA Control 1 Register .........................................................................................................16-14

16.5.4

UART DMA Control 2 Register .........................................................................................................16-14

16.5.5

UART DMA Count .............................................................................................................................16-15

16.5.6

UART Transmit Holding Register.......................................................................................................16-15

16.5.7

UART Receiver Holding Register.......................................................................................................16-15

17. Video Module ........................................................................................................................................................17-1

17.1

Overview ......................................................................................................................................................17-1

17.1.1

Related Pins...........................................................................................................................................17-1

17.2

Interface Requirements.................................................................................................................................17-2

17.2.1

Display Types........................................................................................................................................17-2

17.2.2

Timing Requirements ............................................................................................................................17-5

17.3

Implementation.............................................................................................................................................17-8

17.3.1

Block Diagram ......................................................................................................................................17-8

17.3.2

Video State Machine .............................................................................................................................17-9

17.3.3

Horizontal Counter..............................................................................................................................17-10

17.3.4

Line Counter........................................................................................................................................17-11

17.3.5

DMA Address Generation...................................................................................................................17-11

17.3.6

Video FIFO..........................................................................................................................................17-13

17.3.7

Gray Scale LUT ..................................................................................................................................17-14

17.3.8

Color LUT...........................................................................................................................................17-15

17.3.9

Dithering .............................................................................................................................................17-17

17.3.10 Related Interrupts ................................................................................................................................17-18

17.4

Video Registers...........................................................................................................................................17-19

17.4.1

Video Control 1 Register.....................................................................................................................17-19

17.4.2

Video Control 2 Register.....................................................................................................................17-21

17.4.3

Video Control 3 Register.....................................................................................................................17-21

17.4.4

Video Control 4 Register.....................................................................................................................17-22

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