TMPR3911 datasheet(96/462 Pages) TOSHIBA

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Chapter 3 CPU Module

3-12

3.3.6.8

EntryHi & EntryLo Registers (CP0 register No.10, No.2)

These two registers provide the data pathway through which the TLB is read, written, or

probed. When address translation exceptions occur, these registers are loaded with relevant

information about the address that caused the exception. The format of the EntryHi and EntryLo

EntryLo is the natural form of a Page Table Entry (PTE); however, since PTEs are always

loaded by system software, not by the TX39/H hardware, an operating system can use another

format for memory-resident PTEs.

TLB EntryHi Register (CP0 register No.10)

PID

VPN

Virtual Page Number. Bits 31..12 of virtual address.

PID

Process ID Process ID field. A 6-bit field which lets multiple processes share the TLB while each

process has a distinct mapping of otherwise identical virtual page numbers.

Reserved. Currently ignores writes, returns zero when read.

TLB EntryLo Register (CP0 register No.2)

PFN

Page Frame Number. Bits 31..12 of the physical address. The TX39/H maps a virtual page to PFN.

Non-cacheable. If this bit is set, the page is marked as non-cacheable and the TX39/H directly

accesses main memory instead of first accessing the cache.

Dirty. If this bit is set, the page is marked as “dirty” and therefore writable. This bit is actually a “write-

protect” bit that software can use to prevent alteration of data. If an entry is accessed for a write

operation when the D bit is cleared, the TX39/H causes a TLB Mod trap. The TLB entry is not modified

on such a trap.

Valid. If this bit it set, it indicates that the TLB entry is valid; otherwise, a TLBL or TLBS Miss occurs.

Global. If this bit it set, the TX39/H ignores the PID match requirement for valid translation. In kseg2,

the Global bit lets the kernel access all mapped data without requiring it to save or restore PID

(Process ID) values.

Reserved. Currently ignores writes, returns zero when read.

Figure 3.3.6 The TLB EntryHi & EntryLo Registers

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