TMPR3911 datasheet(99/462 Pages) TOSHIBA

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Chapter 3 CPU Module

3-15

3.3.6.10 The Index Register (CP0 register No.0)

The Index Register is a 32-bit, read/write register, which has 5 bits that index an entry in the

TLB. The most significant bit of the register shows the success or failure of a TLB Probe (tlbp)

instruction (described later in this chapter).

The Index register also specifies the TLB entry that will be affected by the TLB Read (tlbr) and

TLB Write Index (tlbwi) instructions. Figure 3.3.8 shows the format of the Index register.

Index Register

Index

Probe failure. Set to 1 when the last TLBProbe (tlbp) instruction was unsuccessful.

Index

Index to the TLB entry that will be affected by the TLBRead and TLBWrite instruction.

Reserved. Currently ignores writes, returns zero when read.

Figure 3.3.8 The Index Register

3.3.6.11 The Random Register (CP0 register No.1)

The Random Register is a 32-bit register. The format of the Random Register is shown in

Figure 3.3.9. The five-bit Random filed indexes a random entry in the TLB. The TX39/H

decrements the Random field during every machine cycle but constrains the value of this field to

the TLB indexes from 31 to 8 (the counter wraps around from 8 to 31 skipping values 7 through

0).

The TLB Write Random (tlbwr) instruction is used to write the TLB entry that this register

indexes. The first eight entries (0 to 7) are the “safe” entries because a tlbwr instruction can never

replace the contents of these entries. Typically, these eight entries are reserved for use by the

operating system.

Although normal operations never require it, the contents of this register can be read to verify

proper operation of the process. To further simplify testing, the Random field is set to a value of

31 when the TX39/H is reset.

Random Register

Random

A random index with a value ranging from 8 to 31 to a TLB entry.

Reserved. Currently ignores writes, returns zero when read.

Figure 3.3.9 The Random Register

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