TMPR3911 datasheet(103/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-3

4.2

Address Decoder

The Address Decoder provides the decoding for the address space in the system. The Address Decoder

also contains the logic to generate the address signals A[12:0] for the memory devices, along with Address

Re-Mapper logic used to re-direct memory addresses.

4.2.1

System Address Map

The System Address Map is shown in Table 4.2.1. The address space is partitioned to support two

banks (Bank 1 and Bank 0) of DRAM and/or SDRAM, four general purpose 16/32-bit chip selects

(CS3-CS0), four general purpose 16-bit-only chip selects (MCS3-MCS0), two PCMCIA slots (Card 2

and Card 1), and internal function register access. The address space contains two primary regions:

kseg0/kseg1 are only accessible in kernel mode, while kuseg is accessible in either user or kernel mode.

MCS3-MCS0 are available in kuseg space and are thus always available to either user or kernel mode

accesses.

CS3-CS1 are located in both kseg and kuseg space, but accesses in kuseg space can be independently

disabled for each chip select using the ENCS3USER, ENCS2USER, and ENCS1USER control bits in

the Memory Configuration 0 Register. CS0 is used as the chip select for the boot ROM in the system. It

is mapped starting at address $11000000 in kernel space, which will map into the TX39/H boot vector

location at address $1FC00000. CS0 is also mapped in kuseg space to allow access to the ROM by

programs operating in user mode.

Card 1 and Card 2 are mapped into kuseg space for memory accesses and kernel-only space for IO

and Attribute accesses. To access the attribute space in a card, the CARD1IOEN or CARD2IOEN bits

in the Memory Configuration 3 register must be cleared prior to accessing the Card space. For I/O

accesses the CARD1IOEN or CARD2IOEN bits must be set prior to accessing the Card space.

The processor can write to the Mode Registers in the SDRAMs in kernel mode at address $10E00000

and $10F00000 for Bank 0 and Bank 1 SDRAM banks, respectively. Bank 0 and Bank 1 are each

mapped into four different locations. Each location is just an image of the other locations. Each Bank

can contain either DRAM or SDRAM devices, with the only restriction being that Bank 1 cannot

contain SDRAM if Bank 0 contains DRAM.

A system can be built without DRAM or SDRAM and instead can contain SRAM as the main

memory. In this case at least one bank of SRAM should be connected to CS1 and the ENCS1DRAM

control bit in the Memory Configuration 0 Register should be set. Setting this bit will cause CS1 to map

in place of Bank 0 and Bank 1, as shown in Table 4.2.1. This is required because exception vectors are

mapped into physical address 0x0000_0080 (in case of BEU

= 0 in TX39/H core STATUS register),

thus it is required that some memory exist in this region to support exception handling. Accesses to

reserved or non-enabled locations will respond with a Bus Error if the Watch Dog Timer is enabled.

TMPR3911 Datasheet(PDF) 103 Page - Toshiba Semiconductor