TMPR3911 datasheet(105/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-5

4.2.2

Address Generation

The Address Decoder logic generates the A[12:0] address bus for the memory devices. Addresses are

multiplexed on the A[12:0] address bus. For static devices such as CS3-CS0, MCS3-MCS0, Card 2 and

Card 1, the addresses are multiplexed such that Addr[25:13] is provided first-in-time followed by

Addr[12:0], as shown in Figure 4.2.1. Addr[25:13] must be latched with an external latch using the

ALE signal. The latched addresses concatenated with A[12:0] will provide a 26-bit address bus for the

system, HA[25:0].

HA[25:0]

A[12:0]

ALE

Addr[25:13]

Addr[12:0]

TX3911/12

ALE

A[12:0]

HA[25:0]

Figure 4.2.1 ALE Timing

DRAM and SDRAM devices contain multiplexed address buses. Thus, A[12:0] will be directly

connected to the DRAM and SDRAM devices. In order to support a wide range of DRAM and SDRAM

types and configurations, there are control bits in the Memory Configuration 0 Register that provide

software configuration for the Row and Column address bit positions. These control bits are

ROWSEL0[1:0] and COLSEL0[2:0] for Bank 0, and ROWSEL1[1:0] and COLSEL1[2:0] for Bank 1.

Table 4.2.2 shows the position that specific address bits are placed, depending on the configuration of

the control bits. This flexibility in address bit positioning makes it possible to support 4-Mbit, 16-Mbit,

and 64-Mbit DRAM and SDRAM devices with different bus width configurations. The two sets of

control bits make it possible to support different devices in Bank 0 and Bank 1. The “

φ” character in the

table means that this bit position will be a zero and the “X” implies a “don’t care” bit position.

Table 4.2.2 TMPR3912 DRAM and SDRAM Address Mapping

ROW A[12:0]

ROWSEL

COL A[12:0]

COLSEL

18, 17:9

22, 20, 18, 8:1

0000

22, 18, 20, 19, 17:9

19, 18, 8:2

0001

20, 22, 21, 19, 17:9

21, 20, 18, 8:2

0010

22, 23, 21, 19, 17:9

23, 22, 20, 18, 8:2

0011

24, 22, 20, 18, 8:2

0100

18,

φ, X, 8:0

0101

22, X,

φ, 21, 8:0

0110

18,

φ, X, 21, 8:1

0111

22, X,

φ, 23, 21, 8:1

1000

24, 23, 21, 8:2

1001

Example: When ROWSEL[1:0] = 01, the address bits Addr[22], Addr[18], Addr[20], Addr[19] and Addr[17:9] are

outputed to A[12], A[11], A[10], A[9] and A[8:0] pins respectively as row address for DRAM and/or

SDRAM.

When COLSEL[3:0] = 1000, the address bits Addr[22], undefined value, zero data, Addr[23], Addr[21],

and Addr[8:1] are outputed to A[12], A[11], A[10], A[9], A[8], A[7:0] respectively as column address for

DRAM and/or SDRAM.

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