TMPR3911 datasheet(107/462 Pages) TOSHIBA

107 / 462 page

Chapter 4 BIU Module

4-7

4.3

Chip Select Controller

4.3.1

Description

The Chip Select Controller provides the logic required to generate CS3-CS0, MCS3-MCS0, Card 2,

and Card 1 control signals. CS3-CS0 can each independently be set as either 32-bit or 16-bit ports.

MCS3-MCS0, are always 16-bit ports. Card 2 and Card 1 can be set as either 16-bit or 8-bit ports.

The access time for each chip select is individually programmed using the control bits in the Memory

Configuration 1-3 Registers. Also provided for CS3-CS0 and MCS3-MCS0 is separate access time

control for Read Page Mode that can be enabled or disabled independently for each chip select using the

ENCS

χPAGE (χ = 0, 1, 2, 3), ENMCSχPAGE (χ = 0, 1, 2, 3) control bits in the Memory Configuration

3 Register. The Read Page Mode provides burst read capability to support memory devices such as page

mode ROMs. There is separate access time control provided for memory accesses to Card 2 or Card 1,

or IO/Attribute accesses to Card 2 or Card 1. The address inputs for all 32-bit memory devices should

be connected starting with HA[2] and all 16-bit memory devices should be connected starting with

HA[1]. The PCMCIA cards will use all the address bits HA[25:0].

TMPR3911 Datasheet(PDF) 107 Page - Toshiba Semiconductor