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TMPR3911 Datasheet(PDF) 104 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 104 Page - Toshiba Semiconductor |
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104 / 462 page  Chapter 4 BIU Module 4-4 Table 4.2.1 System Address Map (Physical Address) Size Address Segment Devices 16 Mbyte FF00_0000 reserved reserved 1 Gbyte C000_0000 kseg2 reserved 1 Gbyte 7C00_0000 kuseg reserved 64 Mbyte 7800_0000 kuseg MCS3 64 Mbyte 7400_0000 kuseg MCS2 64 Mbyte 7000_0000 kuseg MCS1 64 Mbyte 6C00_0000 kuseg MCS0 64 Mbyte 6800_0000 kuseg Card 2 (Memory) 64 Mbyte 6400_0000 kuseg Card 1 (Memory) 64 Mbyte 6000_0000 kuseg CS3 (if enabled) 64 Mbyte 5C00_0000 kuseg CS2 (if enabled) 64 Mbyte 5800_0000 kuseg CS1 (if enabled) 128 Mbyte (*) 5000_0000 kuseg CS0 (ROM) 128 Mbyte 4800_0000 kuseg reserved 32 Mbyte 4600_0000 kuseg DRAM BANK1 32 Mbyte 4400_0000 kuseg DRAM BANK0 32 Mbyte 4200_0000 kuseg CS1 (if enabled, else DRAM BANK 1) 32 Mbyte 4000_0000 kuseg CS1 (if enabled, else DRAM BANK 0) 512 Mbyte 2000_0000 reserved reserved 240 Mbyte (*) 1100_0000 kseg0, kseg1 CS0 (ROM) 1 Mbyte 10F0_0000 kseg0, kseg1 SDRAM BANK 1 Mode Register 1 Mbyte 10E0_0000 kseg0, kseg1 SDRAM BANK 0 Mode Register 2 Mbyte 10C0_0000 kseg0, kseg1 Internal Function Registers 4 Mbyte 1080_0000 kseg0, kseg1 CS3 4 Mbyte 1040_0000 kseg0, kseg1 CS2 4 Mbyte 1000_0000 kseg0, kseg1 CS1 64 Mbyte 0C00_0000 kseg0, kseg1 Card 2 (I/O or Attribute) 64 Mbyte 0800_0000 kseg0, kseg1 Card 1 (I/O or Attribute) 32 Mbyte 0600_0000 kseg0, kseg1 DRAM BANK1 32 Mbyte 0400_0000 kseg0, kseg1 DRAM BANK 0 32 Mbyte 0200_0000 kseg0, kseg1 CS1 (if enabled, else DRAM BANK 1) 32 Mbyte 0000_0000 kseg0, kseg1 CS1 (if enabled, else DRAM BANK 0) (*) Note: Since external addresses (HA[25:0] are only 26 bit width, memory space which can be used physically is only 64 Mbyte of these CS0 area. Upper 5 bits of internal addresses (Addr[31:27]) are discarded, so the access to the remaining area overlaps to the physical 64 Mbyte area. |
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