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TMPR3911 Datasheet(PDF) 108 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 108 Page - Toshiba Semiconductor

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Chapter 4 BIU Module
4-8
4.3.2
Access Mapping
This section describes the mapping between the byte lanes of the CPU registers (R[ ]) and the byte
lanes of external signals (D[ ]).
Depending upon CPU endianness, the signal names of some pins are reorganized (see Table 4.3.1).
In this section Xl[ ] means X[ ] in little-endian mode, Xb[ ] means X[ ] in big-endian mode. For
example CASl[ ] means CAS[ ] in little-endian mode, and CASb[ ] means CAS[ ] in big-endian
mode.
example:
In case of little-endian, the physical pins [133:145] are named Dl[7:0], whereas in big-endian
case, the same physical pins are named Db[31:24].
Table 4.3.1 Signal Name in each Endian Mode
Pin No.
3911BXB
3912AU-92
3912XB-92
Little-endian
Big-endian
P7, N7, M6,
R7, N6, M5,
R6, P5
133-145
H12-E14
Dl[7:0]
Db[31:24]
N4, R5, N3,
P3, R4, R3,
P1, N2
146-159
E13-E11
Dl[15:8]
Db[23:16]
C7, D7, C8,
A7, B6, D6,
A6, B5
27-16
H1-F3
Dl[23:16]
Db[15:8]
C5, B4, A5,
C4, A4, B3,
A1, A3
14-2
F4-C3
Dl[31:24]
Db[7:0]
E3
195
D6
CASl[0]*
CASb[3]*
E2
197
B5
CASl[1]*
CASb[2]*
D3
198
C5
CASl[2]*
CASb[1]*
E1
199
E6
CASl[3]*
CASb[0]*
C1
207
B2
DQMLl
DQMHb
B1
208
A2
DQMHl
DQMLb
P11
117
L14
CARD1CSL*
CARD1CSL*
(*1)
R10
118
K12
CARD1CSH*
CARD1CSH*
(*1)
R15
107
L11
CARD2CSL*
CARD2CSL*
(*1)
R13
106
N13
CARD2CSH*
CARD2CSH*
(*1)
*1) not affected by endianness
Table 4.3.2, 4.3.3, 4.3.4, and 4.3.5 show the access mapping in little-endian mode, and Table 4.3.6,
4.3.7, 4.3.8, and 4.3.9 shows the access mapping in big-endian mode.
Note that in both little-endian configuration and big-endian configuration, each device is connected to
the same physical pins.



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