VNF9D5F datasheet(55/108 Pages) STMICROELECTRONICS

55 / 108 page

Table 39. Sampling mode

SPCRxx

Sampling mode

STOP mode

START mode

CONTINUOUS mode

FILTERED mode

Synchronous mode

•

Synchronous mode in PWM condition:

–

Sampling is done according to the PWM rising and falling edge (see Figure 26). See Table 39 for

more details about the registers configuration.

–

The sampling priority will be always allocated at higher priority.

•

Registers configuration:

–

SPCR10 = 0h: Synchronous triggered by rising edge on internal PWM. Conversion is executed on

the rising edge of the conversion window (see Figure 26).

–

The ADC real sampling is managed to trigger the sampling point with margin versus falling edge.

–

SPCR10 = 1h: Synchronous triggered by falling edge of the internal PWM signal. Conversion is

executed on the falling edge of the conversion window (see Figure 26).

Figure 26. Sequence of channels

Channel 0

Channel 1

Channel 2

Channel 3

Sampled Channel:

ADC priority stack:

Direct Input Signal

Tend

ADC Sampling point

Asynchronous mode

In asynchronous mode the ADC result register is continuously refreshed, provided that the channel is

commanded on through either the direct input signal or the SOCR register. Conversion is executed during the

complete conversion window except the priority arbitration.

Since the ADC register is continuously refreshed, its conversion priority is always lower than the sampled

channels.

Once the PWM counter will reach a value for which synchronous diagnostic of another channel is requested, the

internal MUX will switch to this channel and serve the ADC sampling request (channels in synchronous mode

have higher priority compared with those in asynchronous mode). Once this sampling will be completed the MUX

will switch back to the asynchronous sampling channel, provided that no higher priority sampling requests from

other channels occur. If two or more channels are configured in asynchronous mode, the MUX will sequentially

switch through those channels, always interrupted when higher priority synchronous sampling requests occur.

The thermal case sampling has always low priority for the ADC conversion and so can be interrupted by any

channel in sample mode.

VNF9D5F

Diagnostic

DS13946 - Rev 8

page 55/108

VNF9D5F Datasheet(PDF) 55 Page - STMicroelectronics

VNF9D5F Datasheet(HTML) 55 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL