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VNF9D5F Datasheet(PDF) 10 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 108 page ![]() Table 4. Frame 1: read (ROM) 0x3F 0x-- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMD OC1 OC0 Address 1 1 1 1 1 1 1 1 DATA1 X(1) X X X X X X X 0 0 0 0 0 0 0 0 DATA2 X X X X X X X X 0 0 0 0 0 0 0 0 1. X = do not care. At least one of these bits must be zero, as 0xFFFF frame is not allowed. The entry to the Fail Safe mode can occur due to the CSN timeout. In this specific case, the following procedure must be executed to leave the Fail Safe mode: • Removing the cause of the CSN stuck • Toggling the CSN pin for a min tSHCH (time to release the SDO line), see parameter in Table 51 • Sending the SPI frames If the above procedure is not respected, the first SPI frame will be rejected and the state transition will fail. Transition from fail-safe mode to normal mode is performed by two special SPI sequences • Frame 1: write “CTRL”0x4000 • Frame 2: write “CTRL”0x0800 Table 5. Frame 1 (write CTRL0x4000) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMD OC1 OC0 Address 0 0 0 1 0 1 0 0 DATA1 GOSTBY UNLOCK Not Used Not Used EN PWM_ TRIG Not Used Not Used 0 1 0 0 0 0 0 0 DATA2 LOCKbit 5 LOCKbit 4 LOCKbit3 LOCKbit2 LOCKbit1 LOCKbit0 PWMSYNC Parity 0 0 0 0 0 0 0 0 Table 6. Frame 2 (write CTRL0x0800) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMD OC1 OC0 Address 0 0 0 1 0 1 0 0 DATA1 GOSTBY UNLOCK Not Used Not Used EN PWM_TRIG Not Used Not Used 0 0 0 0 1 0 0 0 DATA2 LOCKbit 5 LOCKbit 4 LOCKbit3 LOCKbit2 LOCKbit1 LOCKbit0 PWMSYNC Parity 0 0 0 0 0 0 0 0 Transition from normal mode to pre-standby mode using SPI: two frames needed • Frame 1: write “CTRL”0x4800 • Frame 2: write “CTRL”0x8000 VNF9D5F Functional description DS13946 - Rev 8 page 10/108 |
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