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VNF9D5F Datasheet(PDF) 33 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 108 page ![]() Figure 21. Direct input block diagram - valid for 2, 4 and 6 channels device Direct Input 0 Gate Driver Channel 0 OR OR OR OR Gate Driver Channel 1 Gate Driver Channel 2 Gate Driver Channel 3 Direct Input 1 SPI Register : OUTCFGR Output Configuration Register SPI Register : OUTSRx Outputx Status Register SPI Register : SOCR SPI Output Control Register OR Gate Driver Channel 4 OR Gate Driver Channel 5 OUTPUT 5 OUTPUT 4 OUTPUT 3 OUTPUT 2 OUTPUT 1 OUTPUT 4 3 2 1 0 DIENCR 5 DIENCR 4 DIENCR 3 DIENCR 2 DIENCR 1 DIENCR 0 OTP DIENSR DIENSR 5 DIENSR DIENSR DIENSR DIENSR 0 4.4.3 Output switching slopes control Output switching slopes are set by the two bits SLOPECR1, 2 in the OUTCFGCRx register (address from 0x08h to 0x0Dh depending on the channel). The switching slopes are shown in the following table: Table 36. Switching slopes SLOPECRx Channel 0, 1 (V/μs) 00 Standard 01 Fast 10 Faster 11 Fastest VNF9D5F SPI functional description DS13946 - Rev 8 page 33/108 |
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