VNF9D5F datasheet(25/108 Pages) STMICROELECTRONICS

25 / 108 page

Figure 19. SPI read and clear operation

CSN

SDI

SDO

Global Status byte

MSB

LSB

Data byte

MSB

LSB

Command byte

MSB

Address

LSB

Data byte

MSB

LSB

(16 bits)

(8 bits)

Read device information

Specific information can be read but not modified during this mode. Accessible data can be seen in Table 26.

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to

determine which information is read whilst the other two data bytes are "don’t care".

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the

serial clock (SCK). The first byte corresponds to the Global Status byte and the second to the content of the

addressed register and the third byte is 0x00.

Note:

ROM is based on the 8-bit registers, then even if 16 bits are returned, only the second byte contains the

addressed ROM register.

Figure 20. SPI read device information

CSN

SDI

SDO

Global Status byte

MSB

LSB

Data byte

MSB

LSB

Command byte

MSB

Address

LSB

Don’t care

MSB

LSB

(16 bits)

(8 bits)

4.2.3

Special commands

0xFF - SW Reset: set all control registers to default (ROM access)

An OpCode ‘11’ (read device information) addressed at ‘111111’ forces a Software Reset of the device, second

and third bytes are "don't care" provided that at least one bit is zero.

Note:

An OpCode '11' at address '111111' with data field equal to '1111111111111111' on the SPI frame is recognized as

a frame error and SPIE bit of GSB is set.

Table 21. 0xFF: SW_Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Command

OC1

OC0

Address

DATA1

DATA2

VNF9D5F

SPI functional description

DS13946 - Rev 8

page 25/108

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