VNF9D5F datasheet(12/108 Pages) STMICROELECTRONICS

12 / 108 page

Protections

3.1

Thermal case temperature monitoring and pre-warning

Case-temperature is constantly monitored via a 10-bit ADC converter and data is available in the dedicated status

Three different thermal warnings TW1, TW2, TW3 will be mirrored in all the OUTSRx status registers (addresses

from 0x20h to 0x21h), referring to 120 ºC, 130 ºC and 140 ºC frame temperature thresholds, respectively. On top

of that, the content of TW1 bit is reflected in the Global Status Byte (bit1 – TCASE). This bit is set if the frame

temperature is greater than the threshold (120 ºC) and can be used as a global temperature pre-warning. The bit

is cleared automatically when the frame temperature drops below the case-temperature reset threshold (TCR1).

3.2

Junction overtemperature (OT)

If the junction temperature of a channel rises above the shutdown temperature TTSD, an overtemperature (OT)

event is detected.

The channel is switched OFF and the corresponding bit in the Address OUTSRx register - Channel Feedback

Status Register (CHFBSR) is set. As a consequence, the thermal shutdown bit (TSD/PL, bit 4) in the Global

Status Byte and the Global Error Flag are set.

In Normal Mode, each output channel can be either set in latched OFF or time limited auto-restart operation in

case of a junction over temperature event.

•

In latched OFF operation: the output remains switched OFF until the junction temperature falls below the

reset threshold TR. In order to restart the channel, after elapsing of restart delay time (tD_RESTART), the

MCU shall reset the latch-off event by refreshing the programmed value in the dedicated register

(CHLOFFTCR0). The action will clear the corresponding CHLOFFSR bit in Output Status Register

OUTSRx and the bit 4 (TSD/PL bit) in the Global Status Byte.

•

In time limited auto-restart operation: during the programmed time, the output is switched off as described

and switches on again automatically when the junction temperature falls below the reset temperature TR

and restart delay time (tD_RESTART) is elapsed. In order to allow asynchronous diagnostic, the status bit is

latched during OFF state of the channel and it is automatically cleared when the junction temperature falls

below the thermal reset temperature (TRS) of OT detection. It has to be mentioned that the time limited

autorestart (tBLANKING) and restart delay time (tD_RESTART) are contemporarily running, so in case

tBLANKING is programmed with a smaller value as tD_RESTART the channel will stay latched-off after the first

OT intervention. After the programmed time has elapsed, the output remains switched OFF and acts as

latch-off mode.

In fail-safe mode the channel works in auto-restart mode with restart delay time tD_RESTART after each OT event.

Figure 5. Normal mode, short circuit - Programmable Blanking Window (PBW) > tD_RESTART

Iout

OTDIFF_DIAG

OT_DIAG

Latch Off delay→ fixed time window

Power Limitation

ILIMH

Power Limitation

TPBW > TLOFF

Channel is permanently latched off due to PBW function

Latch Off

PBW delay → time window related to parameter in CHLOFFTCR register

OT_FAULT

counter is active

counter is inactive

counter is active

ILIMH

VNF9D5F

Protections

DS13946 - Rev 8

page 12/108

VNF9D5F Datasheet(PDF) 12 Page - STMicroelectronics

VNF9D5F Datasheet(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL