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VNF9D5F Datasheet(PDF) 41 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 41 Page - STMicroelectronics |
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41 / 108 page ![]() CTRL Control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W R/W - R/W W R Address: 0x14h Type: R/W Reset: 0 Description: Control register [15] Go to standby. It is necessary to perform 2 write accesses to enter standby: 1. Write UNLOCK = 1 2. Write GOSTBY = 1 and EN = 0 [14] Unlock bit. UNLOCK bit allows protected SPI transactions. It means that the next SPI communication will automatically clear this bit and prevent any change of protected data (like slope control or Bulb/Led mode for example). As a consequence, modifying a protected data requires to set UNLOCK bit in a first communication and write the protected data during the next communication. [13:12] - [11] Enter normal mode 1 - normal mode 0 - fail-safe mode To enter normal mode: • Write UNLOCK = 1 • Write EN = 1 Note: UNLOCK bit allows protected SPI transactions. Then, the next SPI communication will automatically clear this bit and prevent any change of protected data (like slope control or Bulb/Led mode for example). As a consequence, modifying a protected data requires to set UNLOCK bit in a first communication and write the protected data with the next communication. [10] PWM_TRIG: PWM triggering mode 0: PWM trigger according to the rising edge of PWM period and phase shift configuration 1: PWM trigger according to the falling edge of PWM period and phase shift configuration [9:8] - [7:2] Protected transaction mode: • LOCKEN5: Lock enable for INOMx, TNOMx, and ILIM_LATCHx • LOCKEN4: Lock enable for slope control SLOPECRx • LOCKEN3: Lock enable for Bulb/LED mode CCRx • LOCKEN2: Lock enable for phase shift CHPHAx and PWM_TRIG • LOCKEN1: Lock enable for configurable blanking time CHLOFFTCRx • LOCKEN0: Lock enable for PWM clock synchronization When the bit is set (LOCKENx = 1), it is used to have a protected transaction: • Setting UNLOCK bit • Modify the relevant configuration register • LOCKENx = 0 means reset value - those configuration registers may be altered with a single frame standard write command VNF9D5F SPI functional description DS13946 - Rev 8 page 41/108 |
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